As noted in a previous post, along with finding that Green Mountain Micro (GMM) had created a lowercase modification for the CoCo called “lowerkit”, Eurohard SA also created a lowercase update for the Dragon 200e for the Spanish market, which I think was planned or actually produced as an official part of the Dragon 200e design. Currently, DragonPlus Electronics offers a reproduction of this solution in their store. As I mentioned previously, I did not find a schematic of this solution, though I did find pictures of the PCB on the World of Dragon archives. Since the lowerkit effort had been successful, I decided to reverse engineer the PCB from the pics on the site.
Now, unlike the “lowerkit” option, this PCB used the datasheet recommended 74LS161 counter, and contained fewer components, which made the work easier
The header and the 6847 IC were easy, as was the 74LS161 counter. Based on a note on the DragonPlus web site talking about their effort to create the reproduction, I determined the EPROM was a 2532. Looking at the 74LS244 buffer IC in light of the “lowerkit” design, I surmised that this design used the output enable line on the EPROM to disable it from the VDG data bus, meaning only the data coming from the header data pins needed to be buffered/disabled. This saves an IC over the dual 74ls157 option on “lowerkit”
Also knowing that this design put the counter as the top 4 bits of the EPROM address bus, most of this design was easy to reconstruct. Because the design was tailored to the Dragon, which included a MC6883 Synchronous Address Multiplexer (SAM), none of the MC6847 address lines were bridged to the header except DA0 (as they are not connected to anything on the motherboard. The design took shape, with the exception of the 74LS00 quad NAND gate.
Having the IC in the photo hindered the effort, as there were no traces going into/out of the IC on the top. The reverse shows a few, though, and there a few adjacent pins that appear to be bridged. Working back from how I thought the design should behave, I was able to reconstruct the 74LS00 wiring:
On the 74LS00 (top left IC, reversed pinout on bottom photo), we can follow the trace on pin 1 (top right of IC) to A*/S (Alpha Semigraphics). Likewise, pin 3 ends up at INT*/EXT, which makes sense. If we are requesting alphanumeric glyphs, use the external ROM, otherwise, use the internal. On the other side, pin 13 is connected to A*/G, and pin 9 is connected to the EPROM output enable line (OE*). Finally, pin 8 is connected to the enable line on the 74ls244, which must be low for operation. That makes sense, as either the EPROM OE* should be low OR the buffer enable, but never at the same time. If you squint, you can jsut see that pins 9 and 10 are connected via a trace (the slightly silver part in between). The same thing shows up between 1 and 2, 3 and 4, and 12 and 13. 1/2, 9/10, and 12/13 are all inputs, meaning all 3 of those gates are being used as simple inverters (you can easily turn any NOR and NAND gate into a NOT gate by tying the inputs to the same signal). 3 is an output, and it being tied to 4 means that A*/S is being inverted and sent to a second NAND gate. But, that’s all we can see from the PCB photo. The rest requires inferring what logic is needed.
With pin 9 and 10 going to the EPROM OE* line, that means it should be low when we are wanting alphanumerics. And, we actually only want the EPROM when both A*/S and A*/G are low. But, we know both signals are being inverted for some reason. So, let’s take their inverted versions (A/S* and A/G*) which should both be 1 for external EPROM use. We also know that the inversion of A*/S (pin 3) is being fed to pin 4. Let’s assume the output of the other inversion (pin 11) goes to pin 5 (the other input of the second NAND gate. That means pin 6 will be low when the EPROM needs to be enabled, so OE* should be connected to pin 6. But, we only see it connected to pin 9 and then bridged to pin 10. That means it must connect to pin 6 under the IC:
The only remaining item is address line 7 on the EPROM. Since there are 128 characters in a font (the upper 128 spots are semigraphics), we expect and see the lowest 7 bits of the MC6847 data lines coming from the SAM go to the lowest 7 address lines of the EPROM. We know, because of the font ROM configuration, Address lines 8-11 go to the counter. That leaves address line 7 open. But, if we trace the EPROM pin 1 (address ine 7), we see it goes to the INT*/EXT line from the header. That means that changing the value of that pin on the MC6847 socket (which comes from the PIA) will shift between 2 ROM font sets. That solves the last remaining mystery. Adding in the capacitors, a simple jumper block to select inverse characters, and the design is complete.
However, just like the “lowerkit” design and it’s 2716 EPROM, the 2532 EPROM is hard to find and hard to program. As well, this design is quite a large PCB, making fitment a concern. We should update the design to make it both smaller and shift the EPROM to a newer part, which will no doubt hold more. The larger EPROM then demands some switches to select which font to use. DragonPlus Electronics came to the same conclusion, modifying the original design to take up less space, switching to surface mount parts in the process.
I felt like the design could be shrunk while still keeping through hole parts, though placement would be tight:
I made one “executive” decision on this update, which I am sure will anger some purists. While having free space all self contained in spot of the ROM, I don’t see any useful value for it beyond stowing some explanatory text or copyright, and it makes understanding the ROM data much more difficult. So, I placed the 4 counter address lines at the bottom, meaning each font glyph bitmap will occupy 16 consecutive addresses in the EPROM. Since the files will be Open Source, others can revert that change if it offends them.
Since I didn’t want to find and program a 2532 EPROM, I decided to just manufacture and test the updated PCB, which works perfectly fine:
I can probably squeeze the EPROM closer to the header to reduce PCB size, but the current PCB is 50mm by 58mm (1.95″ x 2.3″), so further optimizations short of moving to SMT is left as an exercise for the reader.
As always, source files, artwork, designs, etc. are available at my GitHub repository: https://github.com/go4retro/dragon200e-lowercase
