I’ve initiated phase 1 of ROM-el production, scheduling the PCB design for production and shipment. ROM-el will be completed in 3 phases:
PCB manufacture and shipment of 2 bare boards
Manual assembly and testing
Release PCB for assembly and shipment
This is typical for new designs, for the following reasons:
Given the low cost of production boards, it’s cheaper to make a production board run instead of an initial prototype board run. In the best case, the board is operational and no prototype board costs are incurred. At worst, the board must be “spun” once more, but the total cost does not exceed a prototype + production run cost.
Shipping 2 boards ahead of time permits verification of the design before assembly. The boards are shipped at no cost by “piggybacking” them on a previous order that is nearing completion.
Normal turnaround is 10 business days (2 calendar weeks), so I expect boards around July 12th.
To save costs in creating the SMT stencil and the boards themselves, I “merged” 4 designs into one set of files for the PCB house using Gerbmerge. I struggled to install the program in Windows, which was unsucessful. The application has some dependencies, one of which requires a C compiler. The Windows install of the dependency assumes Visual C++, which I do not own. After wasting a few hours, I installed on the local Linux server, which was trivial. The application is very straightforward, and I was able to create a minimal merged set of files in a few minutes. Thus, I will be receiving 100 units of:
2364Adapter (simple DIP style 24-28 pin adapter
6540Adapter (CBM-Hackers folks asked for this design, which has not been tested)
The remainder of the 64NIC+ boards have shipped to CCCC for sales and distribution. The 1.0a board sillkscreen looks very professional and calls out not only the Cincinnatti club but also Eric Pratt and Till Harbaum, whose designs I utilized in creating 64NIC+.
The first 20 boards have belatedly arrived from the assembly house. Scheduled to arrive for the C4 EXPO, they were delayed and then sent to my work address instead of the EXPO location.
I am busy making the required minor modification to the 1.0 PCB layout to address issues found during initial testing. These 20 initial boards (+ the 2 prototypes) will be special editions, as the remainder (80) of the units will sport the 1.0a PCB design, which corrects the minor issue with the board. It will be easy to spot a 1.0 board, as much of the silkscreen artwork is missing (an error on my part in creating the files for the PCB house). Still, both the 1.0 and 1.0a boards will function the same.
As announced at the C4 EXPO, I am working with Mark Fellows (Highland IT Solutions) to finalize a licensing agreement for ‘JiffyDOS’ ROM Overlay manufacture and distribution. In addition to hardware ROM enhancement units, I will also offer image downloads for 1541 Ultimate, C64DTV, and emulator users, as well as an amnesty offering for unlicensed copies.
To minimize manual manufacturing processes inherent in the current EPROM-based JiffyDOS offerings, my goal is to utilize the ROM-el EEPROM/FLASH solution for JiffyDOS hardware offerings.
23128 and 23256 ROMs are not as hard to deal with, as 27XXX JEDEC standard EPROMs share the same pinout. However, some of the benefits of the 2364 ROM-el still remain, such as:
Use of 5V programmable FLASH/EEPROM
Can be pre-assembled and field programmed
If used in a switched ROM scenario (one where the upper address bits are toggled on or off via a switch), this design can save a lot of time (most 27256/27512 switched ROM replacement options I’ve seen manually bend the additional address pins over the top of the EPROM and hand solder a resistor to Vcc.)
Thus, I’m considering this unit as well for production. It offers some additional configuration options over the 2364 ROM-el, but retains the ease of assembly and programming of the 2364 ROM-el.
Another project of mine requires a way to replace the 2364 ROMs on Commodore computers, so I started looking for a 2764 to 2364 adapter. After designing one, I determined that DIP EPROMs are starting to get very expensive, so I set about designing a Flash version. My tentative name is ROM-el. Since Flash is considered ROM as well, the name is a bit off, but I liked it, and only the pedantic will probably care.
2 64NIC+ boards arrived on April 20, and I assembled one in the evening. Initial testing with Devia’s NIC-Test was unsuccessful, so I gave up for the night. After work on the 21st, I pored over the schematics and determined I had miscopied a resistor layout from Eric Pratt’s 64NIC design. The resistor must be tied to ground, not Vcc. Dubious that such a small change would make the board work, I nonetheless made the change and …. it did nothing.
I decided I’d ruined one board, so I assembled the second board, taking care to make the resistor mod before plugging it in. Devia’s NIC-Test worked immediately. Later, I tried the apparently ruined board and it also worked, so it appears I did not completely ruin the board.
Given the success, I immediately released the board to production that evening.